Conventional or bulk semiconductor devices are formed in semiconductive material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate increases power consumption, requires higher threshold voltages, and slows the speed at which a device using such transistors can operate (e.g. degrades frequency response). These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance problem and improve frequency response, silicon on insulator technology (SOI) has been gaining popularity. A SOI wafer is formed from a bulk silicon wafer by using conventional oxygen implantation techniques to create a buried oxide layer at a predetermined depth below the surface. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a guassian distribution pattern centered at the predetermined depth to form the buried oxide layer.
An SOI field effect transistor comprises two separated regions consisting of the source and drain regions of the transistor of a first semiconductor conductivity and a channel region between them of the opposite semiconductor conductivity covered by a thin gate insulator and a conductive gate. Conduction in the channel region normally occurs immediately below the gate insulator in the region in which depletion can be controlled by the gate voltage.
A problem associated with reducing the size of an SOI FET structure is a reduction in the length of the channel (distance between the source region and the drain region) degrades FET performance because of a phenomenon known as the short channel effect. More specifically, the decreased channel length permits depletion regions adjacent to the source region and the drain region to extend towards the center of the channel which increases the off state current flow through the channel (current flow when the gate potential is below threshold) and the reduced channel width tends to decrease current flow when the gate potential is above threshold.
Accordingly, there is a strong need in the art for a silicon on insulator field effect transistor structure which can be scaled to sub-micron dimension without significant performance degradation.